常备RV1109

junyunlai · 发表于 2025-2-14 11:47:45

Chapter 1 Introduction
1.1 Overview
RV1109 is a high-performance AI vision processor SoC for IPC, or for other intelligent
vision applications.
It is based on Dual-core ARM Cortex-A7 32-bit core which integrates NEON and FPU.
There is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache.
The build-in NPU supports INT8/INT16 hybrid operation and computing power is up to
1.2TOPs. In addition, with its strong compatibility, network models based on a series of
frameworks such as TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RV1109 also introduces a new generation totally hardware-based 5-megapixel ISP
(image signal processor) and post processor. It implements a lot of algorithm accelerators
usually used in IPC and CVR, such as HDR, 3A functions (AE, AF, AWB), LSC, 3DNR, 2DNR,
sharpening, dehaze, fisheye correction, gamma correction, feature points detection and so
on. All of them are real-time processing. Cooperating with two MIPI CSI (or
LVDS/SubLVDS) and one DVP (BT.601/BT.656/BT.1120) interface, users can build a system
that receives video data from 3 camera sensors simultaneous.
The video encoder embedded in RV1109 supports 5M H.265/H.264 encoding. It also
supports multi-stream encoding, up to one 5M30FPS and one 720P30 simultaneous. With
the help of this feature, the video from camera can be encoded with higher resolution and
stored in local memory and transferred another lower resolution video to cloud storage at
the same time.
The H.264/H.265 video decoder in RV1109 supports 5M for H.264 and H.265.
RV1109 has high-performance external DRAM (DDR3/DDR3L/DDR4/LPDDR3/LPDDR4)
capable of sustaining demanding memory bandwidths.
1.2 Features
The features listed below which may or may not be present in actual product, may be
subject to the third-party licensing requirements. Please contact Rockchip for actual
product feature configurations and licensing requirements.
1.2.1 Application Processor
 Dual-Core Cortex-A7
 Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced
SIMD
 Separately Integrated Neon and FPU
 32KB L1 I-Cache and 32KB L1 D-Cache per Cortex-A7 CPU
 Unified 512KB L2 Cache for Dual-Core Cortex-A7
 TrustZone technology supported
 Separate power domains for CPU core system to support internal power switch and
externally turn on/off based on different application scenario
 PD_CPU0: 1st Cortex-A7 + Neon + FPU + L1 I/D Cache
 PD_CPU1: 2nd Cortex-A7 + Neon + FPU + L1 I/D Cache
 One isolated voltage domain to support DVFS
1.2.2 Video Input Interface
 Interface and video input processor
 Two MIPI CSI/ LVDS/SubLVDS interfaces, 4 lanes each, 2.5Gbps per lane
 One 8/10/12/16-bit standard DVP interface, up to 150MHz input data
 Support BT.601/BT.656 and BT.1120 VI interfaces
 Support the polarity of pixel_clk、hsync、vsync configurable

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[方案] 常备RV1109